Heterogeneous memristive crossbar for in-memory computing

It's been quite a while since scientists are seeking for the ancestor of von Neumann computing architecture. Among the most promising candidates, memristor demonstrates advantageous characteristics, which open new pathways for the exploration of advanced computing paradigms. In this work we propose the design of a novel crossbar geometry, which is heterogeneous in terms of its cross-point devices, allowing for the realization of true in-memory digital logic computations. More specifically, it is a combination of two stacked crossbar arrays with a shared intermediate nanowire layer. The variety of available cross-points types allows the execution of parallel memristive logic computations, where the logic state variable is voltage. Moreover, the utilization of insulating patterns in the crossbar arrays, at the expense of a small area-overhead, permits the simultaneous parallel read/write memory operation of two memory words. Memory/logic operation is determined through control signals driven from the peripheral CMOS-based driving circuitry, which also comprises row/column decoders, tri-state drivers, and summing/ sense amplifiers to allow for the proper programming/reading of the memristive cross-pointsPeer ReviewedPostprint (author's final draft

Cellular Automaton Belousov-Zhabotinsky Model for Binary Full Adder

© 2017 World Scientific Publishing Company. The continuous increment in the performance of classical computers has been driven to its limit. New ways are studied to avoid this oncoming bottleneck and many answers can be found. An example is the Belousov-Zhabotinsky (BZ) reaction which includes some fundamental and essential characteristics that attract chemists, biologists, and computer scientists. Interaction of excitation wave-fronts in BZ system, can be interpreted in terms of logical gates and applied in the design of unconventional hardware components. Logic gates and other more complicated components have been already proposed using different topologies and particular characteristics. In this study, the inherent parallelism and simplicity of Cellular Automata (CAs) modeling is combined with an Oregonator model of light-sensitive version of BZ reaction. The resulting parallel and computationally-inexpensive model has the ability to simulate a topology that can be considered as a one-bit full adder digital component towards the design of an Arithmetic Logic Unit (ALU)

Experimental study of artificial neural networks using a digital memristor simulator

© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.This paper presents a fully digital implementation of a memristor hardware simulator, as the core of an emulator, based on a behavioral model of voltage-controlled threshold-type bipolar memristors. Compared to other analog solutions, the proposed digital design is compact, easily reconfigurable, demonstrates very good matching with the mathematical model on which it is based, and complies with all the required features for memristor emulators. We validated its functionality using Altera Quartus II and ModelSim tools targeting low-cost yet powerful field programmable gate array (FPGA) families. We tested its suitability for complex memristive circuits as well as its synapse functioning in artificial neural networks (ANNs), implementing examples of associative memory and unsupervised learning of spatio-temporal correlations in parallel input streams using a simplified STDP. We provide the full circuit schematics of all our digital circuit designs and comment on the required hardware resources and their scaling trends, thus presenting a design framework for applications based on our hardware simulator.Peer ReviewedPostprint (author's final draft

Crossbar-based memristive logic-in-memory architecture

The use of memristors and resistive random access memory (ReRAM) technology to perform logic computations, has drawn considerable attention from researchers in recent years. However, the topological aspects of the underlying ReRAM architecture and its organization have received less attention, as the focus has mainly been on device-specific properties for functionally complete logic gates through conditional switching in ReRAM circuits. A careful investigation and optimization of the target geometry is thus highly desirable for the implementation of logic-in-memory architectures. In this paper, we propose a crossbar-based in-memory parallel processing system in which, through the heterogeneity of the resistive cross-point devices, we achieve local information processing in a state-of-the-art ReRAM crossbar architecture with vertical group-accessed transistors as cross-point selector devices. We primarily focus on the array organization, information storage, and processing flow, while proposing a novel geometry for the cross-point selection lines to mitigate current sneak-paths during an arbitrary number of possible parallel logic computations. We prove the proper functioning and potential capabilities of the proposed architecture through SPICE-level circuit simulations of half-adder and sum-of-products logic functions. We compare certain features of the proposed logic-in-memory approach with another work of the literature, and present an analysis of circuit resources, integration density, and logic computation parallelism.Peer ReviewedPostprint (author's final draft